SINGAPORE — 20 AUGUST 2013, UNITED STATES — (Marketwired) — 08/19/13 — (“STATS ChipPAC” or the “Company”) (SGX-ST: STATSChP) (SGX: S24), a leading provider of advanced semiconductor packaging and test services, today announced a new milestone in reducing Package-on-Package (PoP) height with its ultra thin technology. STATS ChipPAC has pursued innovative advances in embedded packaging design methodology, process enhancements and cost structure to deliver eWLB-based PoP solutions with an ultra thin package profile height of 0.3mm.
The industry adoption of PoP as a dominant packaging approach in stacking the logic processor and memory into a single solution for advanced mobile phones and tablets has accelerated the need to drive ultra thin package profiles in this technology. Earlier in 2012, STATS ChipPAC utilised eWLB technology to deliver a 30% height reduction in PoP, reducing the overall stacked package height from the industry standard 1.4mm to 1.0mm. Today, through further innovations in eWLB technology, STATS ChipPAC has achieved a 40% height reduction in the bottom PoP architecture to provide an ultra thin z-height of 0.3mm, thereby providing customers with the advantage of having an overall PoP package height as low as 0.8mm with proven board level reliability.
“The emergence of ultra slim devices that are able to deliver exceptional performance continues to grow across the mobility, consumer and computing markets. Our breakthrough technology achievements in package height reduction, increased performance and reliability with eWLB-based PoP solutions enable packaging solutions that provide a competitive edge to substrate-based PoP solutions while remaining cost effective,” said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC. “We have successfully developed best-in-class, ultra thin PoP solutions below 1.0mm to support the continued success of our leading-edge mobility customers and will continue to extend our innovative technology to attain even smaller form factors in semiconductor packaging technology.”
eWLB provides a robust packaging platform supporting ultra high density interconnection and routing of multiple die in very reliable, low-profile, low-warpage packages that are cost effective solutions for baseband processors, RF transceivers, power management components and application processors. For high performance applications such as smartphones and tablets, eWLB technology delivers fine line width and spacing of less than 10um/10um as well as superior electrical performance, providing more design flexibility and a more significant reduction in size than is possible with printed circuit board (PCB) substrate technology.
Dr. Han continued, “While traditional PoP solutions are widely used in the high-end mobility market, demand is accelerating for ultra thin, cost effective packages that have the flexibility to serve a range of applications from mid-range to low-end mobile phones as well as tablets that require significantly higher processor speeds. While PCB substrate technology limits the interconnection density of a PoP package to 200-300 I/O, eWLB-based PoP solutions can deliver beyond 500 I/O in an overall thinner package with a dense vertical interconnection and wider interface to stack memory packages on the top. As we continue to expand the capabilities of eWLB and demonstrate innovative variations with this packaging platform, we are seeing more designs migrating to this technology.”
Certain statements in this release are forward-looking statements that involve a number of risks and uncertainties that could cause actual results to differ materially from those described in this release. Factors that could cause actual results to differ include, but are not limited to, general business and economic conditions and the state of the semiconductor industry; prevailing market conditions; demand for end-use applications products such as communications equipment, consumer and multi-applications and personal computers; decisions by customers to discontinue outsourcing of test and packaging services; level of competition; our reliance on a small group of principal customers; our continued success in technological innovations; pricing pressures, including declines in average selling prices; intellectual property rights disputes and litigation; our ability to control operating expenses; our substantial level of indebtedness and access to credit markets; potential impairment charges; availability of financing; changes in our product mix; our capacity utilisation; delays in acquiring or installing new equipment; limitations imposed by our financing arrangements which may limit our ability to maintain and grow our business; returns from research and development investments; changes in customer order patterns; customer credit risks; disruption of our operations; shortages in supply of key components and disruption in supply chain; inability to consolidate our Malaysia operations into our China operations and uncertainty as to whether such plan will achieve the expected objectives and results; the amount of the business interruption insurance claim due to flooding of the Thailand Plant; loss of key management or other personnel; defects or malfunctions in our testing equipment or packages; rescheduling or cancelling of customer orders; adverse tax and other financial consequences if the taxing authorities do not agree with our interpretation of the applicable tax laws; classification of our Company as a passive foreign investment company; our ability to develop and protect our intellectual property; changes in environmental laws and regulations; exchange rate fluctuations; regulatory approvals for further investments in our subsidiaries; majority ownership by Temasek Holdings (Private) Limited (“Temasek”) that may result in conflicting interests with Temasek and our affiliates; unsuccessful acquisitions and investments in other companies and businesses; labour union problems in South Korea; uncertainties of conducting business in China and changes in laws, currency policy and political instability in other countries in Asia; natural calamities and disasters, including outbreaks of epidemics and communicable diseases; the continued trading and listing of our ordinary shares on the Singapore Exchange Securities Trading Limited (“SGX-ST”). You should not unduly rely on such statements. We do not intend, and do not assume any obligation, to update any forward-looking statements to reflect subsequent events or circumstances.
STATS ChipPAC Ltd. (SGX-ST Code: S24) is a leading service provider of semiconductor packaging design, assembly, test and distribution solutions in diverse end market applications including communications, digital consumer and computing. With global headquarters in Singapore, STATS ChipPAC has design, research and development, manufacturing or customer support offices throughout Asia, the United States and Europe. STATS ChipPAC is listed on the SGX-ST. Further information is available at . Information contained in this website does not constitute a part of this release.
Tham Kah Locke
Vice President of Corporate Finance
Tel: (65) 6824 7788
Fax: (65) 6720 7826
email:
Lisa Lavin
Deputy Director of Marketing Communications
Tel: (208) 867-9859
email:
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