LOS GATOS, CA — (Marketwired) — 09/26/13 —
Controlling power consumption is the greatest challenge for chip designers. In the white paper entitled: “SuVolta-s DDC Technology: A Complementary Technology to ARM Embedded Processors for Power Optimized Application,” SuVolta describes significant power reduction results and operating speed (performance) enhancements demonstrated in a system-on-a-chip (SoC) test chip incorporating ARM Cortex-M0 processors and static random-access memory (SRAM). Elements of the white paper were published in a paper in the proceedings of the IEEE Custom Integrated Circuits Conference (CICC), held in San Jose, California, September 23 – 25, 2013.
The process technology used by the semiconductor industry for the past 40 years — conventional bulk planar CMOS — is hitting active and leakage power limits, and voltage scaling has stagnated at ~1 Volt for the past 10 years. Power dissipation has become the primary architectural limiter for mobile SoCs. The total power consumption in a SoC constrains both the thermal envelope and the battery life of mobile products.
One major implication of this barrier is manifested in the semiconductor industry-s constant struggle to reduce power consumption and increase battery life of mobile devices without sacrificing performance or cost.
Deeply Depleted Channel (DDC) technology and DDC-optimized circuits and design techniques enable scaling (reduction) of two of the most critical transistor parameters — scaling of supply voltage, and scaling of transistor size to the sub-20nm node. DDC technology applies across a wide range of integrated circuit (IC) products, including processors, memories, and SoCs that are critical to today-s mobile products.
SuVolta, Inc.
The white paper can be access on SuVolta-s web site at: .
The white paper is available as of September 26, 2013.
Margo Westfall
SuVolta, Inc.
+1 (408) 429 6058
Steve Jursa
The Hoffman Agency
+1 (408) 975 3029
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