HILLSBORO, OR — (Marketwire) — 09/06/11 — Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced that it is now shipping samples of its MachXO2 PLD family using a 2.5mmx2.5mm 25-ball Wafer Level Chip Scale Package (WLCSP). The MachXO2 devices now combine an extremely — until now unprecedented in the PLD market — with the industry-s lowest power and most feature rich low density PLDs. Built on a low power 65nm process featuring , the MachXO2 family delivers a 3X increase in logic density, a 10X increase in embedded memory and more than a 100X reduction in static power compared to previous generations. With the industry-s most robust PLD functionality, ultra low power and new WLCSP , the MachXO2 devices can now address applications previously not accessible to PLDs.
“WLCSP is a superior packaging solution for markets that demand the smallest possible form factor,” said Mike Orr, Lattice Vice President of Product Development. “WLCSP features outstanding performance for signal integrity, power management and thermal characteristics. WLCSP is also cost effective, reliable and uses standard board mounting processes for simple handling and manufacturability.”
The MachXO2 family leads the industry in providing the lowest power and highest functionality of any PLD family. Now Lattice is extending its lead in the low density PLD market by offering a portfolio of small footprint die/package combinations for the MachXO2 family to be made available throughout 2011, including:
A 2.5mmx2.5mm 25-ball WLCSP, shipping immediately: Die size-defined BGA with 0.4mm solder ball pitch, providing 19 user I/O in a 6.1mm(2) footprint
A 3.2mmx3.2mm 49-ball WLCSP: Die size-defined BGA with 0.4mm solder ball pitch, providing 40 user I/O in a 9.8mm(2) footprint
A 4mmx4mm 64-ball ucBGA: Saw singulated BGA with 0.4mm solder ball pitch, providing 45 user I/O in a 16.0mm(2) footprint
A 8mmx8mm 132-ball ucBGA: Saw singulated BGA with 0.5mm solder ball pitch, providing up to 105 user I/O in a 64.0mm(2) footprint
“We have combined aggressive packaging technologies to deliver some of the smallest PLD footprints ever in the programmable logic industry. When these footprints are combined with the superior functionality and ultra-low power available on the MachXO2 devices, we are able to address a new class of applications not previously available to SRAM-based PLDs,” said Shakeel Peera, Director of Marketing for Silicon and Solutions at Lattice Semiconductor. “There is little doubt that consumer device connectivity and space constraints are moving in opposite directions. These new MachXO2 devices will enable new possibilities for digital logic designers focused on these space constrained applications, without having to sacrifice flexibility or programmability.”
MachXO2 LCMXO2-1200ZE devices in the 25 WLCSP are now available as engineering samples, with production devices scheduled to be available by Q4 2011. All other ultra-low footprint packages mentioned in this news release will be sampling by the end of 2011. Pricing for the LCMXO2-1200ZE 25WLCSP is $0.95 in 100KU volume. For more information about the Lattice MachXO2 PLD family, visit
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Brian Kiernan
Corporate Communications Manager
Lattice Semiconductor Corporation
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