Sidense Qualifies 1T-OTP Memory IP at SMIC 130nm and 110nm Processes
Sidense Now Supports Several Popular SMIC Processes From 40nm to 130nm for IoT and Other Key Market Segments
Sidense Exhibiting and Presenting at TSMC Open Innovation Platform (OIP) Ecosystem Forum
Sidense to Discuss Ultra Low Power OTP Design for the Smart Connected Universe
MEDIA ALERT: Sidense Exhibiting at TSMC 2015 North American Technology Symposiums
OTTAWA, ON and SAN JOSE, CA — (Marketwired) — 03/27/15 –Sidense will be exhibiting at the North American TMSC Technology Symposiums (San Jose, CA, Austin, TX and Boston, MA), discussing its low-cost, secure and reliable 1T-OTP non-volatile memory (NVM) IP, available from 180nm to 20nm including HV and BCD process nodes.Tuesday, April 7, 9:30AM-5:30PM
San Jose McEnery Convention Center
150 West San Carlos Street
San Jose, CA 95113
Booth #201Tuesday, April 14, 9:30AM-5:30PM
Marriott Burlington
Sidense Increases Its Coverage of the Popular 28nm Node
1T-OTP Macros, Targeting the Smart Connected Universe, Meet All of GLOBALFOUNDRIES– Qualifications for 28nm-HPP and 28nm-SLP Processes
MEDIA ALERT: Sidense Exhibiting at TSMC Open Innovation Platform (OIP) Ecosystem Forum
Sidense to Discuss OTP for Mobile Applications
Lattice Ships One Million MachXO2 Programmable Logic Devices
Fastest Customer Adoption in Company History for Innovative Low Cost, Low Power PLD Family
All Members of Lattice-s Award-Winning MachXO2 PLD Family Released to Production
New $29.99 Evaluation Kit Enables Easy Access to Production-Qualified PLD Technology