Verific Design Automation–s Board Member Honored With DATE Fellow Award
Yearly Award to Be Presented to Robert Gardner During DATE–s Opening Ceremonies
Yearly Award to Be Presented to Robert Gardner During DATE–s Opening Ceremonies
Thoroughly Tested Parsers Let Tortuga Logic Focus on Software to Identify Security Vulnerabilities in Hardware Designs
Verific–s Parser Platform Ensures Integration With SystemVerilog and UVM
Double-Digit Revenue Increase From Eight New Licensees, Repeat Business; Continues Technology R&D Efforts